Cadence Launches New RTL AI Agent That Reduces Chip Design Area by 24% and Power Usage by 18%
Cadence Design Systems (CDNS) announced the launch of a new RTL Generation Agent as part of its ChipStack AI Super Agent. The tool is designed to automate aspects of digital chip design using natural-language prompts, enabling users to convert chip specifications directly into register-transfer level (RTL) code and analyze designs more efficiently. The agent reportedly reduces chip design area by 24% and power consumption by 18%, offering significant improvements in performance and efficiency. This advancement is expected to streamline the complex process of semiconductor development, potentially accelerating time-to-market for new chips while reducing costs associated with manual design processes. By integrating AI into its design tools, Cadence aims to enhance productivity across the chip design lifecycle, which could position it more competitively within the growing demand for advanced semiconductors in industries such as automotive and artificial intelligence.
Tickers: $CDNS
Topics: AI Chip Design Semiconductors